1. Field of the Invention
The present invention relates to a semiconductor device having a circuit constructed of a thin film transistor (hereinafter referred to as TFTs) and a method of manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel, and electronic equipment having such an electro-optical device mounted thereon as a part.
It is to be noted that a semiconductor device as used herein throughout the present specification denotes a general device which functions by utilizing semiconductor characteristics, and that electro-optical devices, semiconductor circuits, and electronic equipments are all semiconductor devices.
2. Description of the Related Art
Techniques for structuring a thin film transistor (TFT) using a semiconductor thin film (having a thickness on the order of about several to several hundred nm) formed on a substrate having an insulating surface have been in the spotlight in recent years. Thin film transistors are widely applied to electronic devices such as an IC or an electro-optical device, and in particular, development of the TFT as a switching element of a liquid crystal display device is proceeding rapidly.
In order to obtain high quality images in the liquid crystal display device, an active matrix type liquid crystal display device that utilizes TFTs as switching elements to be connected to respective pixel electrodes which are arranged in matrix is attracting much attention.
It is necessary that the electric potential of an image signal is held in each pixel electrode connected to the TFTs until the next write-in time in order to perform good quality display in the active matrix type liquid crystal display device. Generally, the provision of a storage capacitor (Cs) in each pixel holds the electric potential of the image signal.
Various proposals have been made for the structure and the formation methods of the above stated storage capacitor (Cs). However, from the viewpoint of reliability or simplicity of the manufacturing process, it is preferable that, of the insulating films for structuring a pixel, a gate insulating film of a TFT, which has the highest quality is utilized as a dielectric of the storage capacitor (Cs). Conventionally, as shown in FIG. 18, a capacitor wiring that becomes an upper electrode is first provided by utilizing a scanning line, and then the formation of the storage capacitor (Cs) is carried out by using the upper electrode (capacitor wiring), a dielectric layer (gate insulating film), and a lower electrode (semiconductor film).
Also, from the viewpoint of display performances, there is a demand for giving pixels larger storage capacitors as well as making the aperture ratio higher. Efficient utilization of a back light is improved if each pixel has a high aperture ratio. Consequently, the amount of back light for obtaining a predetermined display luminance can be restrained, and therefore attainment of a power-saving and small scale display device can be achieved. Furthermore, each pixel is provided with a large storage capacitor, thereby improving the characteristic of each pixel in holding display data, to improve the display quality. In addition, in case of point sequential driving of the display device, a signal storage capacitor (sample hold capacitor) is required in the driver circuit side of each signal line. However, with the provision of a large storage capacitor in each pixel, a surface area occupied by the sample hold capacitor can be made smaller, and therefore the display device can be made smaller.
Such demands become problems in proceeding with the progress of making the pitch of each display pixel microscopic which accompanies the progress of making a liquid crystal display device smaller and high definition (increasing the number of pixels).
There is an additional problem in that it is difficult to make a high aperture ratio and a large storage capacitor compatible with each other in the above stated conventional pixel structure.
An example in which a conventional pixel structure having the size of a pixel formed to 19.2 μm in accordance with the design rule of Table 1 is shown in FIG. 18.
TABLE 1Si layer: minimum size = 0.8 μm, minimum spacing = 1.5 μmGate electrode: minimum size = 1.0 μm, minimum spacing = 1.5 μmScanning line: minimum size = 1.5 μm, minimum spacing = 1.5 μmContact hole of signal line and Si layer: minimum size = 1.0 μm□margin of the contact hole and the Si layer = 1.0 μmminimum spacing of the contact hole and the scanning (gateelectrode) line = 1.3 μmSignal line: minimum size = 1.5 μm, minimum spacing = 1.5 μmmargin of the contact hole and the signal line = 1.3 μmPixel size: 19.2 μm□Pixel TFT: L = 1.5 μm, W = 0.8 μm, single gateScanning line: minimum size of the wiring width = 1.0 μmScanning line: minimum size of the wiring width at a portion ofoverleaping Si layer = 1.5 μmCapacitor wiring: minimum size = 2.0 μm
A characteristic of the conventional pixel structure is that two wirings (a scanning line and a capacitor wiring) are arranged parallel to each other in relation to the continuous formation of the two respective wirings, the scanning line and the capacitor wiring. In FIG. 18, reference numeral 10 denotes a semiconductor film, 11 denotes a scanning line, 12 denotes a signal line, 13 denotes an electrode, and 14 denotes a capacitor wiring. Note that FIG. 18 is a simplified top view of the pixel, and therefore a pixel electrode that is connected to the electrode 13 and a contact hole that reaches the electrode 13 are both not shown in the figure.
Thus, in the case of structuring the storage capacitor with a upper electrode (capacitor wiring), a dielectric layer (gate insulating film), and a lower electrode (semiconductor film), all the circuit elements (a pixel TFT, a storage capacitor, a contact hole, ect.) necessary for structuring a circuit of the pixel become elements relevant to a gate insulating film. Accordingly, these elements constituting the circuit elements are arranged almost planarly within each pixel.
Therefore, it is crucial to efficiently layout the circuit elements that are necessary for constructing the circuit of the pixel in order to attain both a high aperture ratio and a large storage capacitor of each pixel within the regulated pixel size. In other words, from the fact that all the circuit elements are in connection with the gate insulating film, it can be said that it is essential to improve the efficiency of utilizing the gate insulating film.
Thus, from the above perspective, an efficient planar layout of the example of the circuit structure of a pixel of FIG. 18 is shown in FIG. 19. In FIG. 19, reference numeral 21 denotes a single pixel region, 22 denotes a pixel opening region, 23 denotes a storage capacitor region, 24 denotes an A region, and 25 denotes a portion of the TFT and a contact region.
With respect to the area of the pixel opening region 22 which is 216.7 μm2 (aperture ratio of 5.8.8%) as shown in FIG. 19, it is composed of the areas of the storage capacitor region 23 which is 64.2 μm2, the portion of the TFT and the contact region 25 which is 42.2 μm2, and the A region 24 which is 34.1 μm2.
The A region 24 is a segregation region of the scanning line and the capacitor wiring which originated from the fact that a wiring portion for mutually connecting a region that functions as a gate electrode of a TFT, the scanning line and the capacitor wiring are arranged parallel to each other. The gate insulating film of the A region is not rendered its original function, becoming a cause of reducing the efficiency of layout.
Further, in the case of the above structure, there is a problem in that the demand for a capacitor wiring resistance has become strict.
In a normal liquid crystal display device drive, the writing-in of the electric potential of the image signal to the plurality of pixels connected to each scanning line is performed consecutively in the scanning line direction (in the case of the point sequential drive) or all at the same time (in the case of the linear sequential drive).
In terms of arranging the capacitor wiring and the scanning line parallel to each other in the pixel structure as stated above, the plurality of pixels connected to the respective scanning lines are connected to a common capacitor wiring. Therefore, opposing electric currents for a plurality of pixels corresponding to the pixel writing-in electric current continuously or simultaneously flow in the common capacitor wiring. In order to avoid a reduction in display quality caused by the electric potential variation of the capacitor wiring, it is necessary to sufficiently lower the capacitor wiring resistance.
However, widening the width of the wiring for lowering the resistance of the capacitor wiring means that the surface area of the storage capacitor is enlarged while the aperture ratio of the pixel is reduced.